cs.AR提交于 2026-10-07已译

面向异构边缘 SoC 上 AI 推理负载的硬件配置选择与映射联合智能体设计空间探索

Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs

Geetha Prasuna Yarramneni · Surya Selvam · Wilfried Haensch · Anand Raghunathan

中文摘要

现代边缘系统级芯片(SoC)集成了异构处理单元(PU),如 CPU、GPU、NPU,各自具有不同的性能与能耗特征。在实时延迟与能耗约束下部署 AI 推理负载,需要同时将负载映射到合适的 PU 并配置每个 PU(例如选择活跃核心数与运行频率)。这一联合空间呈组合爆炸,穷举搜索不可行。既有设计空间探索(DSE)工作大多采用黑盒优化(BBO),如进化搜索,每次评估仅返回延迟、能耗等聚合指标;近期基于大语言模型(LLM)的 DSE 也依赖同样稀疏的反馈。这种反馈既不揭示设计空间的内在结构,也不解释某一设计选择为何表现如此,使 LLM 的推理能力未被充分利用。本文提出 TraceDSE,一种面向异构 SoC 上 AI 推理负载的智能体 DSE 流程,通过迭代的提议-批评环路进行联合工作负载映射与 PU 配置选择,并以更丰富的系统执行轨迹(trace)作为反馈。LLM 提议智能体生成候选映射与 PU 配置以供硬件评估;LLM 批评智能体配备可编程的轨迹分析工具,用于定位瓶颈并提出有针对性的优化建议。该环路对每个设计点提供更深层洞察,从而实现更高质量的决策与更高效的搜索。在 Intel Meteor Lake SoC 上针对四个 AI 推理负载(复杂度各异的模型以及一个多模型流水线)的实验中,TraceDSE 稳定优于两种当前最优的 BBO 工具:相比 NSGA-II 帕累托前沿超体积提升最多 35%,相比贝叶斯优化提升最多 68%,同时所需硬件评估次数减少约 6 至 9 倍。

关键要点

01问题:异构边缘 SoC 上 AI 推理的负载映射与 PU 配置构成组合爆炸的联合设计空间,黑盒优化与既有 LLM DSE 仅依赖延迟、能耗等稀疏聚合反馈,无法解释设计选择背后的原因。
02方法:TraceDSE 采用基于 LLM 的提议-批评智能体环路,提议智能体生成候选映射与配置,批评智能体结合可编程轨迹分析工具识别瓶颈并提出针对性优化,以执行轨迹作为更丰富的反馈。
03结果:在 Intel Meteor Lake 上四个 AI 推理负载上,TraceDSE 相比 NSGA-II 帕累托超体积最多提升 35%,相比贝叶斯优化最多提升 68%,且硬件评估次数减少约 6-9 倍。
04价值:通过对每个设计点提供深层洞察,该方法在保持黑盒优化可比性的同时,释放 LLM 推理能力以提升搜索效率与解的质量。
05适用范围:实验覆盖单模型(复杂度各异)与多模型流水线场景,验证了在异构 CPU/GPU/NPU 上的通用性。

解读

尚无解读。

原始英文摘要

arXiv:2610.07191v1 Announce Type: cross Abstract: Modern edge Systems-on-Chip (SoCs) integrate heterogeneous processing units (PUs) such as CPUs, GPUs, and NPUs, each with distinct performance and energy characteristics. Deploying AI inference workloads on them under real-time latency and energy constraints requires jointly mapping workloads to PUs and configuring each PU (e.g., selecting the number of active cores and the operating frequency). This joint space grows combinatorially, making exhaustive search infeasible. Most prior work on design space exploration (DSE) applies black-box optimization (BBO) such as evolutionary search, where each evaluation returns only aggregate metrics such as latency and energy. Recent LLM-guided DSE relies on the same sparse feedback. We observe that this limits its efficiency: it offers no insight into the design space or the reasons a design choice performs the way it does, and it leaves the reasoning abilities of LLMs largely unused. We present TraceDSE, an agentic DSE flow that performs joint workload mapping and PU configuration selection for AI inference on heterogeneous SoCs. TraceDSE is an iterative proposer-critic loop driven by richer feedback in the form of system execution traces. The LLM proposer agent generates candidate mappings and PU configurations for hardware evaluation. The LLM critic agent, equipped with programmatic trace-analysis tools, analyzes the traces to identify bottlenecks and suggest targeted refinements. This loop yields deeper insight into each design point, higher-quality decisions, and a more effective search. Across four AI inference workloads (models of varying complexity and a multi-model pipeline) on an Intel Meteor Lake SoC, TraceDSE consistently outperforms two state-of-the-art BBO tools, improving Pareto frontier hypervolume by up to 35% over NSGA-II and up to 68% over Bayesian optimization, while requiring ~6-9x fewer hardware evaluations.