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VLA-HWBench:VLA 模型在边缘硬件上运行时的耗时去向

VLA-HWBench: Where the Time Goes When VLA Models Run on Edge Hardware

Borui Xu · Hongshi Tan · Wenqi Jiang · Bingsheng He · Ming Wu · Jason Zeng · et al.

中文摘要

视觉—语言—动作(VLA)模型正日益部署在机器人搭载的边缘设备上,推理延迟会制约闭环控制,但如何协同设计模型、推理软件与边缘硬件以实现实时推理仍不明确。现有工作多只报告任务成功率,且对动作生成策略、推理阶段划分及同一模型上的优化比较有限。该研究在 NVIDIA Jetson AGX Thor 和 AMD Ryzen AI Max+ PRO 395 上,评测18个开放VLA模型及多种后端,并将推理拆分为7个阶段。结果显示,动作生成策略比模型规模更重要,在19种Jetson配置中的14种占主导;Jetson与AMD上的延迟差异分别达82倍和157倍,参数规模最多只能解释15%的延迟方差。少量flow-matching步骤生成长动作块的模型可跟上控制频率,逐token解码则不能。4-bit权重核融合仅支持$\pi_{0.5}$和GR00T N1.7且仅限Jetson,但比PyTorch配合torch.compile快2.6—2.9倍;GR00T N1.7调用的CPU预处理占比由12%升至39%。优化后,Jetson仅在处理少量token的阶段受内存带宽限制,其余阶段受未融合内核、主机CPU串行预处理等软件因素限制。

关键要点

  1. 01现有评测缺少实时性视角,且未在同一模型上充分比较推理优化。
  2. 02在Jetson与AMD上评测18个开放VLA模型,采用7阶段推理分解。
  3. 03动作生成策略影响大于模型规模,参数规模最多解释15%的延迟方差。
  4. 044-bit权重核融合使$\pi_{0.5}$和GR00T N1.7提速2.6—2.9倍,但支持范围有限。
  5. 05低延迟部署需少迭代动作生成,并兼顾高内存带宽与快速主机CPU。

解读

尚无解读。

原始英文摘要

arXiv:2610.34717v1 Announce Type: new Abstract: Vision--language--action (VLA) models increasingly run on edge devices aboard robots, where inference latency constrains closed-loop robot control. However, it remains unclear how to design VLA models, their inference software and edge hardware so that robots can run VLA inference in real time. Most VLA models report only task success, while prior studies cover limited action-generation strategies, divide inference into at most three stages, and lack comparisons of inference optimizations on the same models.benchmarking 18 open VLA models across released and alternative backends on NVIDIA Jetson AGX Thor and AMD Ryzen AI Max+ PRO 395, with a seven-stage inference breakdown. Our study reveals three insights. First, action-generation strategy matters more than model size. It dominates 14 of 19 Jetson configurations, latency varies by $82\times$ on Jetson and $157\times$ on AMD, and parameter count explains at most 15% of latency variance. Models that generate long action chunks in a few flow-matching steps keep up with control, whereas token-by-token decoding does not. Second, kernel fusion with 4-bit weights helps most, running $\pi_{0.5}$ and GR00T N1.7 2.6--2.9$\times$ faster than PyTorch with \texttt{torch.compile}, but it exists for only these two models and only on the Jetson. Optimization also moves the time to the stages it shortens least, as CPU preprocessing grows from 12\% to 39\% of the GR00T N1.7 call. Third, after optimization, memory bandwidth limits only the stages that process few tokens on the Jetson, such as the denoising steps, whereas software limits all other stages, from unfused kernels to serial preprocessing on the host CPU. Overall, low-latency edge VLAs should use few action-generation iterations, inference software should extend kernel fusion and low-bit weights to more models and platforms, and edge hardware needs high memory bandwidth and a fast host CPU.

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